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型号: 74LS165
厂商: Fairchild Semiconductor Fairchild Semiconductor
描述: 8-bit parallel In/serial output shift registers
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August 1986  
Revised March 2000  
DM74LS165  
8-Bit Parallel In/Serial Output Shift Registers  
General Description  
Features  
Complementary outputs  
Direct overriding (data) inputs  
Gated clock inputs  
This device is an 8-bit serial shift register which shifts data  
in the direction of QA toward QH when clocked. Parallel-in  
access is made available by eight individual direct data  
inputs, which are enabled by a low level at the shift/load  
input. These registers also feature gated clock inputs and  
complementary outputs from the eighth bit.  
Parallel-to-serial data conversion  
Typical frequency 35 MHz  
Typical power dissipation 105 mW  
Clocking is accomplished through a 2-input NOR gate, per-  
mitting one input to be used as a clock-inhibit function.  
Holding either of the clock inputs HIGH inhibits clocking,  
and holding either clock input LOW with the load input  
HIGH enables the other clock input. The clock-inhibit input  
should be changed to the high level only while the clock  
input is HIGH. Parallel loading is inhibited as long as the  
load input is HIGH. Data at the parallel inputs are loaded  
directly into the register on a HIGH-to-LOW transition of the  
shift/load input, regardless of the logic levels on the clock,  
clock inhibit, or serial inputs.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS165M  
DM74LS165WM  
DM74LS165N  
M16A  
M16B  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Inputs  
Internal  
Shift/ Clock Clock Serial Parallel Outputs Output  
QA QB  
QH  
Load Inhibit  
A...H  
a...h  
X
L
H
H
H
H
X
L
X
L
X
X
H
L
a
b
h
QA0 QB0 QH0  
L
X
H
L
QAn QGn  
QAn QGn  
L
X
H
X
X
X
QA0 QB0 QH0  
H = HIGH Level (steady state)  
L = LOW Level (steady state)  
X = Don't Care (any input, including transitions)  
↑ = Transition from LOW-to-HIGH level  
a...h = The level of steady-state input at inputs A through H, respectively.  
Q
Q
, Q , Q = The level of Q , Q , or Q , respectively, before the  
B0 H0 A B H  
A0  
indicated steady-state input conditions were established.  
, Q = The level of Q or Q , respectively, before the most recent  
An  
Gn  
A
G
transition of the clock.  
? 2000 Fairchild Semiconductor Corporation  
DS006399  
www.fairchildsemi.com  
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