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Image AD9854
型号: AD9854
厂商: Analog Devices Inc Analog Devices Inc
标准:
分类: 半导体
描述: cmos 300 mhz quadrature complete-dds
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CMOS 300 MHz Quadrature  
Complete-DDS  
a
AD9854  
FEATURES  
300 MHz Internal Clock Rate  
Integrated 12-Bit Output DAC  
3.3 V Single Supply  
Multiple Power-Down Functions  
Single-Ended or Differential Input Reference Clock  
Small 80-Lead LQFP Packaging  
Ultrahigh-Speed, 3 ps RMS Jitter Comparator  
Excellent Dynamic Performance: 80 dB SFDR @ 100 MHz  
(?1 MHz) AOUT  
4
?
 to 20
?
 Programmable Reference Clock Multiplier  
Dual 48-Bit Programmable Frequency Registers  
Dual 14-Bit Programmable Phase Offset Registers  
12-Bit Amplitude Modulation and Programmable  
Shaped On/Off Keying Function  
APPLICATIONS  
Agile, Quadrature L.O. Frequency Synthesis  
Programmable Clock Generator  
FM Chirp Source for Radar and Scanning Systems  
Test and Measurement Equipment  
Commercial and Amateur RF Exciter  
Single Pin FSK and PSK Data Interface  
Linear or Nonlinear FM Chirp Functions with Single  
Pin Frequency “Hold” Function  
GENERAL DESCRIPTION  
The AD9854 digital synthesizer is a highly integrated device  
that uses advanced DDS technology, coupled with two internal  
high-speed, high-performance quadrature D/A converters and a  
comparator to form a digitally-programmable I and Q synthesizer  
function. When referenced to an accurate clock source, the  
AD9854 generates highly stable, frequency-phase-amplitude-  
programmable sine and cosine outputs that can be used as an  
agile L.O. in communications, radar, and many other applications.  
The AD9854’s innovative high-speed DDS core provides 48-bit  
frequency resolution (1 microHertz tuning steps). Phase trunca-  
Frequency-Ramped FSK  
<25 ps RMS Total Jitter in Clock Generator Mode  
Automatic Bidirectional Frequency Sweeping  
SIN(x)/x Correction  
Simpli?ed Control Interface  
10 MHz Serial, 2-Wire or 3-Wire SPI-Compatible or  
100 MHz Parallel 8-Bit Programming  
tion to 17 bits assures excellent SFDR. The AD9854’s circuit  
(continued on page 14)  
FUNCTIONAL BLOCK DIAGRAM  
DAC R  
SET  
DIGITAL  
MULTIPLIERS  
300MHz  
DDS  
DIFF/SINGLE  
SELECT  
INV.  
SINC  
12-BIT "I"  
DAC  
I
ANALOG OUT  
ANALOG OUT  
FILTER  
4
?
–20
?
 
REF CLK  
MULTI-  
REFERENCE  
CLOCK IN  
PLEXER  
INV.  
SINC  
FILTER  
12-BIT  
"Q" OR  
CONTROL DAC  
MUX  
Q
PHASE/OFFSET  
MODULATION  
SYSTEM  
CLOCK  
RAMP-UP/-DOWN  
CLOCK/LOGIC  
AND  
SHAPED  
ON/OFF KEYING  
FSK/BPSK/HOLD  
DATA IN  
FREQUENCY TUNING WORD/PHASE WORD  
MULTIPLEXER AND RAMP START STOP LOGIC  
MULTIPLEXER  
12-BIT CONTROL  
DAC DATA  
48-BIT  
FREQUENCY  
TUNING WORD  
14-BIT PHASE  
OFFSET/  
MODULATION  
12-BIT  
AM  
MOD  
AD9854  
ANALOG IN  
CLOCK OUT  
BIDIRECTIONAL  
I/O UPDATE  
PROGRAMMING REGISTERS  
READ  
PROGRAMMABLE RATE  
AND UPDATE CLOCKS  
I/O PORT BUFFERS  
WRITE  
COMPARATOR  
MASTER  
RESET  
+V  
GND  
SERIAL/PARALLEL  
SELECT  
S
6-BIT ADDRESS  
OR SERIAL  
8-BIT PARALLEL  
LOAD  
PROGRAMMING  
LINES  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
? Analog Devices, Inc., 1999  
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