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TNT4882的详细信息

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TNT4882  
Single-Chip IEEE 488.2 Talker/Listener ASIC  
Generic Pin Con?guration  
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
DATA7  
DATA6  
GND  
NDACN  
NRFDN  
GND  
81  
82  
83  
84  
85  
86  
87  
DAVN  
EOIN  
DATA5  
DATA4  
GND  
GND  
VDD  
DATA3  
DATA2  
DATA1  
GND  
DIO4N 88  
DIO3N  
GND  
89  
90  
91  
92  
93  
94  
95  
96  
97  
TNT4882  
Generic Pin Configuration  
DIO2N  
DIO1N  
GND  
VDD  
DATA0  
RDY1  
GND  
VDD  
XTAL0  
XTAL1  
GND  
VDD  
GND  
INTR  
KEYCLKN 98  
DACKN  
KEYDQ  
99  
DRQ  
KEYRSTN  
100  
BURST_RDN  
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30  
Figure 3. TNT4882 Generic Pin Con?guration  
Generic Pin Description  
All pins with names that end in ‘N are active low; all others are active high. All input (I) and bidirectional (I/O) pins have an internal pull-up  
resistor between 50 k? and 150 k?.  
Note: You can also see the Hardware Considerations chapter of the TNT Programmer Reference Manual” (P/N 320724-01) for more  
information.  
Pin No.(s)  
Name(s)  
Type  
O
Description  
1
BBUS_OEN  
DATA15-8  
Asserts when DATA7-0 (B bus) is enabled for output  
2,3,5,6,7,9,10,11  
I/O  
Upper 8 bits of bidirectional three-state data bus for transfer of commands, data, and status  
between TNT4882 and CPU – also known as the A bus  
14  
ABUSN  
I
I
Enables register accesses through the A bus (DATA15-8) – DATA15 is the most signi?cant bit  
Determines which register to access during a read or write operation  
Asserts when DATA15-8 (A bus) is enabled for output  
19-15  
20  
ADDR4-0  
ABUS_OEN  
TADCS  
O
O
O
O
I
21  
Asserts when the TNT4882 is an active or addressed IEEE 488 Talker (TADS, TACS, or SPAS)  
Asserts in two-chip mode during a NAT4882 register I/O access  
Asserts when in DTAS or when the auxiliary trigger software command is issued  
Asserting this pin pages in the page-in registers in the 7210 mode  
Asserts when the TNT4882 is in a remote state (REMS or RWLS)  
Rearranges the order of the registers when asserted and in 9914 mode  
Asserts when the FIFO is ready for burst access  
22  
CPUACC  
TRIG  
23  
26  
PAGED  
28  
REM  
O
I
29  
SWAPN  
FIFO_RDY  
BURST_RDN  
30  
O
I
31  
When asserted, places the TNT4882 in a burst read mode, in which the ?rst word in the  
FIFO is always driven on the TNT4882 data bus – words are removed from the FIFOs at  
each rising edge of RDN – see reference manual for details  
Asserts to request a DMA transfer cycle  
32  
33  
34  
38  
DRQ  
O
I
DACKN  
INTR  
Enables FIFO accesses during a DMA transfer cycle  
O
O
Asserts when one or more of the unmasked interrupt conditions becomes true  
Asserts during an I/O access to indicate that the read data is available or that the write  
data has been latched – asserts immediately on an access to Turbo488 registers or in  
one-chip mode  
RDY1  
50,49,47,46,  
44,43,42,39  
DATA7-0  
I/O  
Lower eight bits of bidirectional three-state data bus for transfer of commands, data, and  
status between TNT4882 and CPU – also known as the B bus – DATA7 is the most signi?cant bit  
Table continued on page 4  
National Instruments  
3
Phone: (512) 794-0100 ? Fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com  
TNT4882  
Single-Chip IEEE 488.2 Talker/Listener ASIC  
Table continued from page 3  
Pin No.(s)  
Name(s)  
DCAS  
NC  
Type  
O
Description  
51  
52  
53  
Asserts when the device clear state machine is in DCAS  
Leave this pin unconnected  
O
MODE  
I
Determines whether the TNT4882 powers up in 7210 or 9914 emulation mode –  
High = 7210 mode, Low = 9914 mode  
55  
62  
63  
CSN  
I
I
I
Chip Select enables I/O transfers between the CPU and the TNT4882  
Enables register accesses through the B bus (DATA7-0)  
Enables the contents of the registers selected by ADDR 4:0 and CSN or the FIFOs to  
appear on the data bus selected by ABUSN and BBUSN  
Latches data on the bus selected by ABUSN and BBUSN into an internal TNT4882 register  
on the trailing (rising) edge of WRN  
BBUSN  
RDN  
64  
WRN  
I
66  
LADCS  
O
I
Asserts when the TNT4882 is addressed as a Listener  
Holds the TNT4882 in its idle state  
67  
RESETN  
DIO8-1N  
71,74,77,80,88,  
89,91,92  
70,73,76,79,  
81,82,84,85  
I/O  
8-bit bidirectional IEEE 488 data bus  
RENN, ATNN, SRQN,  
IFCN, NDACN, NRFDN,  
DAVN, EOIN  
XTAL0  
I/O  
IEEE 488 control signals  
95  
O
I
Output of crystal circuit – use only for driving a quartz crystal  
Crystal oscillator input – drive with a 40 MHz CMOS input level clock signal  
Strobes data to or from a DS1204 electronic key  
Transmits serial data between the TNT4882 and a DS1204 key  
Resets a DS1204 key  
96  
XTAL1  
98  
KEYCLKN  
O
I/O  
O
_
99  
KEYDQ  
100  
KEYRSTN  
4,8,13,25,27,35,37  
41,45,48,54,56,57,  
59,61,65,68,72,75,  
78,83,86,90,93,97  
12,24,36,40,58,  
60,69,87,94  
GND  
Ground pins – 0 V  
VDD  
_
Power pins – +5 V (±5%)  
ISA Pin Con?guration  
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
DATA7  
DATA6  
GND  
NDACN  
NRFDN  
GND  
81  
82  
83  
84  
85  
86  
87  
DAVN  
EOIN  
DATA5  
DATA4  
GND  
GND  
VDD  
DATA3  
DATA2  
DATA1  
GND  
DIO4N 88  
DIO3N  
GND  
89  
90  
91  
TNT4882  
ISA Pin Configuration  
DIO2N  
VDD  
DIO1N 92  
DATA0  
IOCHRDY  
AEN_N  
VDD  
GND  
VDD  
93  
94  
95  
96  
97  
XTAL0  
XTAL1  
GND  
GND  
INTR  
KEYCLKN 98  
DACKN  
KEYDQ  
99  
DRQ  
KEYRSTN  
100  
ADDR9  
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30  
Figure 4. TNT4882 ISA Pin Con?guration  
4
National Instruments  
Phone: (512) 794-0100 ? Fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com  
TNT4882  
Single-Chip IEEE 488.2 Talker/Listener ASIC  
ISA Pin Description  
All input (I) and bidirectional (I/O) pins have an internal pull-up resistor between 50 k? and 150 k?. Pins with names that end in “N” are  
active low signals – all others are active high. Open-collector outputs are type OC.”  
Note: You can also see the Hardware Considerations chapter of the TNT Programmer Reference Manual” (P/N 320724-01) for more  
information.  
Pin No.(s)  
Name(s)  
Type  
O
Description  
1
D7_0_OEN  
DATA15-8  
Asserts when DATA7-0 bus is enabled for output – may be left unconnected  
Upper eight bits of bidirectional three-state data bus for transfer of commands,  
data, and status between TNT4882 and CPU – can connect directly to the AT bus –  
DATA15 is the most signi?cant bit  
2,3,5,6,7,9,10,11  
I/ O  
14  
BHEN_N  
ADDR4-0  
ADDR9-5  
I
I
I
Enables access to upper eight bits of data bus when asserted  
Determines which register will be accessed during an I/ O access  
Determines if an I/ O address is within the range occupied by the TNT4882 –  
the chip is selected and an I/ O access occurs when ADDR9-5 match SW9-5 and  
AEN_N is asserted  
19-15  
31,30,29,28,26  
20  
D15_8_OEN  
NC  
O
O
I
Asserts when DATA15:8 bus is enabled for output – may be left unconnected  
Leave unconnected  
21,54  
52,51,23,22,55  
SW9-5  
DRQ  
Determines the base address of the TNT4882  
32  
33  
34  
37  
38  
O
I
Asserts to request a DMA transfer cycle  
DACKN  
INTR  
Enables FIFO accesses during a DMA transfer cycle  
O
I
Asserts when one or more of the unmasked interrupt conditions becomes true  
Enables I/ O accesses to the TNT4882  
AEN_N  
IOCHRDY  
OC  
When the TNT4882 is not accessed, this open-collector signal is not driven, and a  
pull-up resistor on the system board keeps it pulled high – at the start of some  
TNT4882 accesses, the TNT4882 may drive it low, then pull it high again during the  
cycle to indicate that the TNT4882 is ready for the CPU to end that cycle  
Lower eight bits of bidirectional three-state data bus for transfer of commands, data,  
and status between TNT4882 and CPU – can connect directly to the AT bus – DATA7  
is the most signi?cant bit  
50,49,47,46,44,  
43,42,39  
DATA7-0  
I/ O  
53  
62  
63  
64  
MODE  
I
I
I
I
Forces the TNT4882 to 7210 (high) or 9914 (low) emulation mode on a hardware  
reset – may be left unconnected  
SENSE_8_16N  
IORN  
Pull this pin low to tell the TNT4882 that it is connected to a 16-bit bus – leave it  
unconnected if the TNT4882 is connected to an 8-bit bus  
Drives the contents of the register selected by ADDR4-0 on the data bus when the  
TNT4882 is selected  
IOWN  
The value on the data bus is latched into the register selected by ADDR4-0 on the  
rising edge of IOWN when you select the TNT4882  
66  
IOCS16N  
RESET  
OC  
I
Driven low during an access to the upper data bus  
67  
Causes a hardware reset and holds the TNT4882 in its idle state while asserted  
8-bit bidirectional IEEE 488 data bus  
71,74,77,80,88,  
89,91,92  
70,73,76,79,81,  
82,84,85  
DIO8-1N  
I/ O  
RENN, ATNN, SRQN,  
IFCN, NDACN, NRFDN,  
DAVN, EOIN  
XTAL0  
I/ O  
IEEE 488 control signals  
95  
O
I
Output of crystal circuit – use only for driving a quartz crystal  
Crystal oscillator input – drive with a 40 MHz CMOS input level clock signal  
Strobes data to or from the DS1204 electronic key  
Transmits serial data between the TNT4882 and a DS1204 key  
Resets a DS1204 key  
96  
XTAL1  
98  
KEYCLKN  
O
99  
KEYDQ  
I/ O  
O
100  
KEYRSTN  
4,8,13,25,27,35,41,  
45,48,57,61,65,68,72,  
75,78,83,86,90,93,97  
12,24,36,40,56,58,  
59,60,69,87,94  
GND  
Ground pins – 0 V  
VDD  
Power pins – +5 V (±5%)  
National Instruments  
5
Phone: (512) 794-0100 ? Fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com  
TNT4882  
Single-Chip IEEE 488.2 Talker/Listener ASIC  
TNT4882 Register Map  
NAT4882 Registers  
7210 Mode  
Read Register  
9914 Mode  
9914 Mode Swapped  
ADDR4-0  
00000  
00010  
00100  
Hex Offset  
Write Register  
CDOR  
Read Register  
Write Register  
IMR0  
Read Register  
Write Register  
CDOR  
0
2
DIR  
ISR1  
ISR2  
ISR0  
ISR1  
DIR  
IMR1  
IMR1  
CPTR  
SPSR  
PPR  
4
IMR2  
ADSR  
IMR2  
SPMR  
EOSR  
BCR  
ACCR  
AUXCR  
ADR  
00110  
01000  
6
SPSR  
ADSR  
SPMR  
ADMR  
BSR  
ISR2  
ISR2  
ADR  
IMR2  
EOSR  
BCR  
ACCR  
AUXCR  
IMR0  
IMR1  
8
ADSR  
01010  
01100  
01110  
10001  
10011  
10101  
10111  
11011  
11101  
11111  
A
C
CPTR  
ADR0  
ADR1  
DSR  
AUXMR  
ADR  
SPSR  
SPMR  
BSR  
CPTR  
PPR  
ISR0  
E
EOSR  
SH_CNT  
HIER  
DIR  
CDOR  
ISR1  
11  
13  
15  
17  
1B  
1D  
1F  
MISC  
KEYREG  
DCR  
CSR  
SASR  
ISR0  
BSR  
IMR0  
BCR  
Turbo488 Registers (Same in All Modes)  
ADDR4-0  
01001  
01011  
01101  
10000  
10010  
10100  
10110  
11000  
11001  
11010  
11100  
11110  
Hex Offset  
Read Register  
CNT2  
CNT3  
Write Register  
CNT2  
9
B
CNT3  
D
HSSEL  
CFG  
10  
12  
14  
16  
18  
19  
1A  
1C  
1E  
STS1  
IMR3  
IMR3  
CNT0  
CNT1  
FIFOB  
FIFOA  
ISR3  
CNT0  
CNT1  
FIFOB  
FIFOA  
CCR  
STS2  
TIMER  
CMDR  
TIMER  
Special Registers Only Accessible in ISA Pin Con?guration  
ADDR4-0  
00101  
00111  
Hex Offset  
Read Register  
Write Register  
5
7
ACCWR  
INTR  
Notes on Register Map  
1. For complete register descriptions, see the TNT4882  
corresponding paged-in register. The two readable paged-in  
registers, the 9914 mode SPSR and ISR2, are both paged in  
whenever any one of the four writable paged-in registers is  
paged in. When you write the clear page-in command to the  
AUXCR, all paged-in registers are paged out again and are no  
longer accessible.  
Programmer Reference Manual” (320724-01)  
2. Some of the 7210 mode registers, such as the ISR1, have  
the same names as some of the 9914 mode registers. The  
7210 mode registers are NOT the same as their 9914 mode  
counterparts. Be sure to refer to the appropriate bit map for  
the chip emulation mode you are using when programming  
these registers.  
4. There are several unused bytes in the address space of the  
TNT4882. These addresses are reserved for adding new  
features to the chip. You should not map any external  
hardware into these addresses or access them at any time, as  
this may cause compatibility problems with future versions of  
the TNT4882.  
3. The shaded registers are paged-in registers.” Paged-in  
registers only exist in 9914 mode. Writing to the address of the  
9914 mode ADSR normally does not access any registers.  
Writing one of four page-in commands to the AUXCR changes  
all subsequent writes to that address to that of the  
6
National Instruments  
Phone: (512) 794-0100 ? Fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com  
TNT4882  
Single-Chip IEEE 488.2 Talker/Listener ASIC  
Hardware Interfacing – ISA Mode TNT4882  
GPIB  
AT(ISA) Bus  
Connector  
TNT4882  
NC  
NC  
NC  
BALE  
SA19-16  
LA23-17  
SD15-0  
SA9-0  
DATA15-0  
DIO8N  
DIO7N  
DIO6N  
DIO5N  
DIO4N  
DIO3N  
DIO2N  
DIO1N  
ADDR9-0  
NC  
NC  
NC  
NC  
SMEMR*  
SMEMW*  
MEMR*  
MEMW*  
SBHE*  
AEN  
IOCHRDY  
RESET  
IOW*  
BHEN_N  
AEN_N  
IOCHRDY  
RESET  
IOWN  
NC  
NC  
NC  
MEMCS16*  
NOWS*  
RENN  
IFCN  
REFRESH*  
NDACN  
NRFDN  
DAVN  
EOIN  
IOR*  
IOCS16*  
IORN  
IOCS16N  
NC  
NC  
MASTER16*  
IOCHK*  
ATNN  
SRQN  
DACK*7-5  
DRQ7-5  
DACKN  
DRQ  
IRQ (3-7,9,10-12,14,15)  
INTR  
NC  
NC  
BCLK  
OSC  
XTAL0  
XTAL1  
NC  
SENSE_8_16N  
40 MHz CMOS  
OSCILLATOR  
NC  
TC  
NC  
NC  
NC  
D15_8_OEN  
D7_0_OEN  
MODE  
Connect DACKN, DRQ, and  
INTR to one of the available  
lines on the AT bus.  
NC  
NC  
NC  
KEYRSTN  
KEYDQ  
SW9  
SW8  
SW7  
SW6  
SW5  
NC  
The TNT4882 is selected when  
KEYCLKN  
the binary value on these pins  
matches that on ADDR9-5.  
Connecting them to ground  
causes the corresponding  
NC  
NC  
}
address lines to be compared to  
zero; leaving them unconnected  
causes those address lines to be  
compared to one. (Base I/O  
address 2C0 hex shown.)  
GPIB  
PC/XT Bus  
Connector  
TNT4882  
NC  
NC  
NC  
BALE  
SA19-16  
LA23-17  
SD7-0  
DATA7-0  
ADDR9-0  
DIO8N  
DIO7N  
DIO6N  
DIO5N  
DIO4N  
DIO3N  
DIO2N  
DIO1N  
SA9-0  
NC  
NC  
NC  
NC  
SMEMR*  
SMEMW*  
MEMR*  
MEMW*  
AEN  
IOCHRDY  
RESET  
IOW*  
AEN_N  
IOCHRDY  
RESET  
IOWN  
RENN  
IFCN  
NC  
NC  
REFRESH*  
IOCHK*  
NDACN  
NRFDN  
DAVN  
EOIN  
IOR*  
IORN  
ATNN  
SRQN  
DACK*3-1  
DRQ3-1  
IRQ7-2  
DACKN  
DRQ  
INTR  
NC  
NC  
BCLK  
OSC  
SENSE_8_16N  
NC  
XTAL0  
XTAL1  
NC  
40 MHz CMOS  
OSCILLATOR  
NC  
TC  
NC  
NC  
NC  
NC  
DATA15-8  
D15_8_OEN  
D7_0_OEN  
MODE  
Connect DACKN, DRQ, and  
INTR to one of the available  
lines on the PC bus.  
NC  
NC  
NC  
KEYRSTN  
KEYDQ  
SW9  
SW8  
SW7  
SW6  
SW5  
NC  
The TNT4882 is selected  
KEYCLKN  
when the binary value on  
these pins matches that on  
ADDR9-5. Connecting  
them to ground causes the  
corresponding address lines  
to be compared to zero;  
NC  
NC  
}
leaving them unconnected  
causes those address lines  
to be compared to one. (Base  
I/O address 2C0 hex shown.)  
Figure 5. PC/XT and AT (ISA) Bus to ISA Mode TNT4882  
National Instruments  
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TNT4882  
Single-Chip IEEE 488.2 Talker/Listener ASIC  
ISA Pin Con?guration Byte Lane Table  
This table shows which byte lane accesses the TNT4882 internal  
registers during an I/ O access when you use the ISA pin  
configuration. All combinations of ADDR4-1, SENSE_8_16N,  
and BHEN_N not shown in this table are illegal. You should not  
apply these combinations to the TNT4882 while the chip is  
selected. The accessed register is determined only by ADDR4-0,  
not SENSE_8_16N or BHEN_N.  
SENSE_8_16N BHEN_N  
ADDR4-0  
11000  
11000  
XXXX1  
XXXX1  
XXXX0  
XXXX0  
XXXX0  
XXXX0  
XXXX1  
XXXX1  
IORN  
0
IOWN  
DATA15-8  
FIFOA  
DATA7-0  
FIFOB  
FIFOB  
Not Driven  
Ignored  
Read  
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
FIFOA  
0
Read  
1
Written  
0
Not Driven  
Ignored  
Not Driven  
Ignored  
Not Driven  
Ignored  
1
Written  
Read  
0
1
Written  
Read  
0
1
Written  
8
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TNT4882  
Single-Chip IEEE 488.2 Talker/Listener ASIC  
Hardware Interfacing – Generic Mode TNT4882  
GPIB  
TNT4882-AQ  
(GENERIC)  
CPU (80186)  
DRQ  
RDY1  
RRN  
DRQ0  
ARDY  
RD  
DIO8N  
DIO7N  
DIO6N  
DIO5N  
DIO4N  
DIO3N  
DIO2N  
DIO1N  
WR  
WRN  
INTR  
INT0  
RESET  
BHE  
RESETN  
ABUSN  
RENN  
IFCN  
AD0  
BBUSN  
NDACN  
NRFDN  
DAVN  
EOIN  
DACKN  
CSN  
ATNN  
SRQN  
Decode  
AD15-0  
ALE  
74573  
74245  
ADDR4-0  
DATA15-8  
NC  
XTAL0  
XTAL1  
40 MHz CMOS  
OSCILLATOR  
DEN  
DT/R  
NC  
NC  
NC  
KEYRSTN  
KEYDQ  
KEYCLKN  
DATA7-0  
CPUACC  
73245  
NC  
PAGED  
SWAPN  
BURST_RDN  
FIFO_RDY  
MODE  
NC  
NC  
NC  
NC  
NC  
NC  
TADCS  
LADCS  
NC  
NC  
NC  
REM  
TRIG  
DCAS  
ABUS_OEN  
BBUS_OEN  
NC  
NC  
Figure 6. Intel CPU to Generic Mode TNT4882  
Generic Pin Con?guration Byte Lane Table  
This table shows which byte lanes will access TNT4882 registers  
during I/O accesses.  
ABUSN  
BBUSN  
ADDR4-0  
11000  
D15-8  
FIFOB  
unused  
FIFOA  
used  
D7-0  
unused  
FIFOB  
FIFOB  
unused  
used  
0
1
0
0
1
1
0
0
1
0
11000  
11000  
XXXXX*  
XXXXX*  
unused  
*Any address except 11000  
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TNT4882  
Single-Chip IEEE 488.2 Talker/Listener ASIC  
Generic Mode DC Characteristics  
Parameter  
Supply voltage  
Voltage input low  
Voltage input high  
Symbol  
Min  
4.75  
-0.5  
2.0  
Max  
5.25  
0.8  
Unit  
V
V
Notes  
V
DD  
V
IL  
V
IH  
V
CC  
V
Voltage output low  
V
OL  
0.0  
0.4  
V
Voltage output high  
Supply current  
Output current low  
V
IDD  
IOL  
2.4  
V
V
mA  
mA  
OH  
DD  
90  
24  
50 mA, typical  
V
OL = 0.4 V  
DATA15-0, LADCS, DRQ, INTR, RDY1  
Output current low  
IOL  
8
mA  
V
OL = 0.4 V  
BBUS_OEN, ABUS_OEN, TADCS,  
CPUACC, REM, TRIG, DCAS, CIC  
FIFO_RDY  
IOL  
IOL  
4
2
mA  
mA  
V
OL = 0.4 V  
V = 0.4 V  
OL  
Output current low  
KEYDQ, KEYRSTN, KEYCLKN  
DIO8-1N, IFCN, SRQN, EOIN, ATNN,  
RENN, DAVN, NRFDN, NDACN  
Output current high  
DATA15-0, LADCS, DRQ, INTR, RDY1  
Output current high  
IOL  
IOH  
IOH  
48  
mA  
V = 0.4 V  
OL  
-12  
-24  
-4  
mA  
mA  
mA  
V
OH = V -0.5 V  
DD  
V
OH = 2.4 V  
V
OH = V -0.5 V  
DD  
BBUS_OEN, ABUS_OEN, TADCS,  
CPUACC, REM, TRIG, DCAS  
FIFO_RDY  
-8  
-2  
-4  
-1  
-2  
mA  
mA  
V
OH = 2.4 V  
IOH  
IOH  
IOH  
V
OH = V -0.5 V  
DD  
V
OH = 2.4 V  
Output current high  
mA  
mA  
mA  
V
OH = V -0.5 V  
DD  
KEYDQ, KEYRSTN, KEYCLKN  
DIO8-1N, IFCN, SRQN, EOIN, ATNN,  
RENN, DAVN, NRFDN, NDACN  
Input leakage current – all pins  
Output leakage current – all pins  
V
OH = 2.4 V  
16  
V
OH = 2.4 V  
I
±10  
±10  
μA  
μA  
V
DD = 5.5 V  
IH  
IOZ  
V
DD = 5.5 V  
Generic Mode Capacitance  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Notes  
Pin capacitance  
C
50  
pF  
DIO8-1N, RENN, ATNN, IFCN, SRQN, DAVN, EOIN, NDACN, NRFDN  
Pin capacitance all other pins  
C
3.6  
pF  
Generic Mode AC Characteristics  
Commercial  
Industrial  
Parameter  
Symbol  
tAS  
tRD  
tDF  
tRW  
tRR  
tAH  
tDU  
tDR  
tWS  
tWH  
tCS  
tCH  
tDS  
tDH  
tCPU  
tARDY  
Min  
24  
Max  
Min  
27  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address setup to RDN = 0, WRN = 0  
Data delay from RDN = 0, CSN = 0 (one-chip mode access)  
Data ?oat from RDN = 1  
RDN pulsewidth (I/0 access)  
RDN recovery width  
Address hold from RDN = 1, WRN = 1  
DRQ unassertion  
Data delay from RDN = 0, DACKN = 0  
Data setup to WRN = 1  
71  
40  
78  
44  
71  
40  
0
78  
44  
0
78  
40  
86  
44  
14  
0
0
0
0
16  
0
0
0
0
Data hold from WRN = 1  
CSN setup to RDN or WRN  
CSN hold from RDN or WRN  
DACKN setup to RDN or WRN  
DACKN hold from RDN or WRN  
RDN or WRN to CPUACC (two-chip mode NAT4882 access only)  
RDN or WRN to RDY1 assert  
Two-chip mode NAT4882 access  
Other accesses  
RDN or WRN to RDY1 unassert  
WRN pulse width (DMA access)  
RDN pulse width (DMA access)  
0
0
26  
29  
10  
25  
22  
10  
28  
25  
clock periods  
ns  
ns  
ns  
ns  
tURDY  
tWP  
tRP  
40  
40  
44  
44  
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TNT4882  
Single-Chip IEEE 488.2 Talker/Listener ASIC  
Generic Mode AC Characteristics Waveforms  
ABUSN,  
BBUSN,  
ADDR4-0  
tAS  
tAH  
CSN  
tCS  
tCH  
tRW  
RDN  
tDF  
tRD  
DATA  
tURDY  
tARDY  
RDY1  
tCPU  
tCPU  
CPUACC??  
??  
CPUACC asserts during two-chip mode  
NAT4882 accesses only  
Figure 7. CPU Read  
DRQ  
t
DU  
DACKN  
t
t
t
RP  
DH  
DS  
RDN  
t
DF  
t
DR  
DATA15-0  
RDY1  
t
RDYQ  
t
URDY  
Figure 8. DMA Read  
ABUSN,  
BBUSN,  
ADDR4-0  
tAS  
tCS  
tAH  
tCH  
CSN  
tWP  
WRN  
tWH  
tWS  
DATA  
tURDY  
tARDY  
RDY1  
tCPU  
tCPU  
CPUACC??  
??  
CPUACC asserts during two-chip mode  
NAT4882 accesses only  
Figure 9. CPU Write  
Waveforms continued on page 12  
National Instruments 11  
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TNT4882  
Single-Chip IEEE 488.2 Talker/Listener ASIC  
Waveforms continued from page 11  
DRQ  
tDU  
DACKN  
tDS  
tDH  
WRN  
tWH  
DATA15-0  
tWS  
Figure 10. DMA Write  
ISA Mode DC Characteristics  
Parameter  
Supply voltage  
Symbol  
Min  
4.75  
-0.5  
2.0  
Max  
5.25  
0.8  
Unit  
V
Notes  
V
DD  
Voltage input low  
Voltage input high  
Voltage output low  
Voltage output high  
Supply current  
V
IL  
V
V
IH  
V
CC  
V
V
OL  
0.0  
0.4  
V
V
OH  
2.4  
V
V
DD  
90  
24  
I
DD  
mA  
mA  
50 mA, typical  
Output current low  
DATA15-0  
I
OL  
V
OL = 0.4 V  
DRQ, INTR, IOCS16, IOCHRDY  
Output current low  
D7_0_OEN  
I
16  
8
mA  
mA  
mA  
V
OL = 0.4 V  
OL = 0.4 V  
OL = 0.4 V  
OL  
Output current low  
D15_8_OEN, TP_INTWTN  
Output current low  
KEYDQ, KEYRSTN, KEYCLKN  
Output current low  
DIO8-1N, RENN, ATNN, IFCN, SRQN,  
DAVN, EOIN, NDACN, NRFDN  
Output current high  
DATA15-0  
I
OL  
V
I
OL  
2
V
I
OL  
48  
mA  
mA  
V
OL = 0.4 V  
I
OH  
-12  
V
OH = V -0.5 V  
DD  
DRQ, INTR  
-24  
-8  
mA  
mA  
V
OH = 2.4 V  
Output current high  
D7_0_OEN  
I
OH  
V
OH = V -0.5 V  
DD  
-16  
-4  
mA  
mA  
V
OH = 2.4 V  
Output current high  
I
OH  
V
OH = V -0.5 V  
DD  
D15_8_OEN,  
TP_INTWTN  
-8  
-1  
mA  
mA  
V
OH = 2.4 V  
Output current high  
I
OH  
V
OH = V -0.5 V  
DD  
KEYDQ, KEYRSTN,  
KEYCLKN  
-2  
mA  
mA  
V
OH = 2.4 V  
Output current high  
DIO8-1N, RENN, ATNN, IFCN, SRQN,  
DAVN, EOIN, NDACN, NRFDN  
Input leakage current – all pins  
Output leakage current – all pins  
I
-16  
V
OH = 2.4 V  
OH  
I
IH  
±10  
±10  
mA  
mA  
V
DD = 5.5 V  
I
OZ  
V
DD = 5.5 V  
12 National Instruments  
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TNT4882  
Single-Chip IEEE 488.2 Talker/Listener ASIC  
ISA Mode Capacitance  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Notes  
Pin capacitance  
C
3.6  
pF  
DATA15-0, DRQ, INTR, IOCS16N,  
IOCHRDY, ADDR6  
Pin capacitance  
C
C
3.0  
3.5  
pF  
pF  
D7_0_OEN, D15_8_OEN, TP_INTWTN,  
KEYDQ, KEYRSTN, KEYCLKN, ADDR4,  
ADDR8, ADDR9  
Pin capacitance  
BHEN_N, ADDR3-0, ADDR5, ADDR7,  
DACKN, AEN_N, MODE, TESTMODE,  
PWBSEL2-0, SW9, SENSE_8_16N,  
IORN, IOWN, RESET  
Pin capacitance  
C
50  
pF  
DIO8-1N, RENN, ATNN, IFCN, SRQN,  
DAVN, EOIN, NDACN, NRFDN  
ISA Mode AC Characteristics  
Parameter  
Symbol  
Min  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Notes  
ADDR9-0 setup to IORN, IOWN  
ADDR9-0 hold from IORN, IOWN  
DACKN setup to IORN, IOWN  
DACKN hold from IORN, IOWN  
Data setup time to IOWN rising  
Data hold time from IOWN rising  
IORN low pulse width  
tAS  
tAH  
tDS  
30  
0
0
tDH  
20  
22  
0
tSU  
tWH  
tRPWL  
tRPWH  
tWPWL  
tWPWH  
tTD  
100  
42  
100  
100  
20  
IORN high pulse width  
IOWN low pulse width  
IOWN high pulse width  
IORN or IOWN held from IOCHRDY  
DRQ unassertion time  
tDU  
73  
48  
80  
80  
Due to FIFO full/ empty  
DRQ unassertion time  
tDU  
Due to byte count reached  
Data access time from IORN falling, DMA  
Data access time from IORN falling, I/ O  
Data hold time from IORN rising  
Data ?oat time from IORN rising  
IOCS16N assertion after valid address  
IOCS16N negation after invalid address  
IOCHRDY negation from IORN or IOWN  
IOCHRDY release after IORN or IOWN  
tDACC  
tACC  
tRH  
0
tDF  
30  
30  
tDEC  
tDECN  
tRDYN  
tRDY  
20  
40  
350  
ISA Mode AC Characteristics Waveforms  
ADDR9-0, AEN_N  
tAH  
tAS  
tRPWL  
IORN  
tRPWH  
DATA15-0  
tACC  
tRH  
tDEC  
tDF  
IOCS16N  
tRDY  
tTD  
tRDYN  
tDECN  
IOCHRDY  
Figure 11. I/O Read Access  
Waveforms continued on page 14  
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TNT4882  
Single-Chip IEEE 488.2 Talker/Listener ASIC  
Waveforms continued from page 13  
ADDR9-0, AEN_N  
tAH  
tAS  
tWPWL  
IOWN  
tWPWH  
DATA15-0  
tSU  
tWH  
tDEC  
IOCS16N  
IOCHRDY  
tRDY  
tTD  
tDECN  
tRDYN  
Figure 12. I/O Write Access  
DRQ  
t
DU  
DACKN  
t
t
t
RPWL  
DH  
DS  
IORN  
t
RPWH  
DATA15-0  
t
t
RH  
DACC  
t
DF  
Figure 13. DMA Read Access  
DRQ  
t
DU  
DACKN  
t
t
t
DH  
DS  
WPWL  
IOWN  
t
WPWH  
DATA15-0  
t
t
SU  
WH  
Figure 14. DMA Write Access  
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TNT4882  
Single-Chip IEEE 488.2 Talker/Listener ASIC  
Absolute Maximum Ratings  
Property  
Supply voltage, V  
Range  
Units  
V
- 0.5 to + 7.0  
- 0.5 to VCC + 0.5  
- 0.5 to VCC + 0.5  
- 55 to 150  
DD  
Input voltage, V  
V
IN  
Output voltage, V  
V
OUT  
Storage temperature, T  
? C  
STG  
23.90 ±0.25  
3.40 (MAX.)  
20.00 ±0.10  
18.85  
2.80 ±0.25  
0.23 ±0.13  
PIN 80  
PIN 51  
PIN 81  
PIN 50  
0.65  
14.00 ±0.10  
12.35  
+0.08  
–0.02  
PIN 1 INDEX  
0.15  
17.90 ±0.25  
0.22 (MIN)  
0.38 (MAX)  
0° –7°  
PIN 31  
DETAIL A  
PIN 100  
PIN 1  
PIN 30  
0.80 ±0.15  
SEE DETAIL A  
FRONT VIEW  
SIDE VIEW  
NOTES:  
1. All dimensions are shown in millimeters.  
2. Unless otherwise specified, all dimensions are nominal.  
3. When converting from millimeters to inches, four significant digits  
to the right of the decimal point are necessary.  
Figure 16. Mechanical Data  
LAND PATTERN  
.075  
1.90  
PIN 1  
.980  
24.9  
.013  
.330  
Note:  
20 x 30 Lead Pattern  
.0256  
0.65  
.745  
18.9  
Figure 17. Recommended Land Pattern (not to scale)  
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TNT4882  
Single-Chip IEEE 488.2 Talker/Listener ASIC  
Technical Support  
Seminars/Training  
National Instruments strives to provide you with quality technical Free and fee-paid seminars are presented several times a year in  
assistance worldwide. We currently offer electronic technical cities around the world. Comprehensive, fee-paid training  
support along with our technical support centers staffed by courses are available at National Instruments offices or at  
Applications Engineers.  
customer sites. Call for training schedules.  
Access information from our Web site at www.natinst.com  
Our FTP site is dedicated to 24-hour support, with a collection of For More Information  
?les and documents to answer your questions. Log on to our  
Internet host at ftp.natinst.com  
Contact National Instruments for Application Notes such as:  
”Using the TNT4882 in a MC68340 System“  
”Factors to Consider When Clocking the TNT4882 at  
Frequencies Less than 40 MHz“  
You can fax questions to our Applications Engineers anytime  
at (800) 328-2203 or (512) 683-5678. Or, you can call from  
8:00 a.m. to 6:00 p.m. (central time) at (512) 795-8248.  
Internationally, contact your local of?ce. National Instruments  
”Porting a 9914 GPIB Design to Use the TNT4882“  
sponsors a wide variety of group activities, such as user group Ordering Information  
meetings at trade shows and at large industrial sites. Our users TNT4882-BQ  
?
also receive our quarterly Instrumentation Newsletter with the latest  
information on new products, product updates, application tips,  
and current events. In addition, sign up for NI News, our electronic  
news service at www.natinst.com/news  
TNT4882 Developer Kit..........................................776866-01  
Includes 2 TNT4882 ASICs, PC AT evaluation board, ESP-488TL  
source code software, and documentation.  
TNT4882 Programmer Reference Manual..............320724-01  
Warranty  
Part Number Legend  
All National Instruments data acquisition, computer-based  
instrument, VXIbus, and MXIbus products are covered by a one-  
year warranty. GPIB hardware products are covered by a  
two-year warranty from the date of shipment. The warranty  
covers board failures, components, cables, connectors, and  
switches, but does not cover faults caused by misuse. The owner  
may return a failed assembly to National Instruments for repair  
during the warranty period. Extended warranties are available  
at an additional charge.  
a
b
c
d
e
TNT  
4882  
B
Q
a. Family name TNT = Single-chip, high-speed,  
GPIB Talker/Listener interface  
b. Device-number 4882 = IEEE 488.2 compatible  
c. Reserved  
d. Revision  
e. Package type Q = Quad ?at pack  
Information furnished by National Instruments is believed to  
be accurate and reliable. National Instruments reserves the right  
to change product speci?cations without notice.  
*000000A-01*  
340570D-01  
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? Copyright 1999 National Instruments Corporation. All rights reserved. Product and company names listed are trademarks or trade names of their respective companies.  
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