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Image XC6SLX45T-2FGG484C
型号: XC6SLX45T-2FGG484C
厂商: Xilinx Inc
标准:
分类: 集成电路嵌入式 - FPGA(现场可编程门阵列)
描述: IC fpga 296 I/O 484fbga
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XC6SLX45T-2FGG484C的详细信息

Datasheets:
Spartan-6 Family Overview:
Spartan-6 FPGA Datasheet:
Product Photos:
XC6SLX25T-2FGG484C:
484-FBGA:
Product Training Modules:
S6 Family Overview:
PCN Design/Specification:
FG(G) and BG(G) Wire Bond 25/Jan/2013:
Standard Package : 60
Category: Integrated Circuits (ICs)
Family: Embedded - FPGAs (Field Programmable Gate Array)
Series: Spartan? 6 LXT
Number of LABs/CLBs: 3411
Number of Logic Elements/Cells: 43661
Total RAM Bits: 2138112
Number of I/O: 296
Number of Gates: -
Voltage - Supply: 1.14 V ~ 1.26 V
Mounting Type: Surface Mount
Operating Temperature: 0°C ~ 85°C
Package / Case: 484-BBGA
Supplier Device Package: 484-FBGA (23x23)
Dynamic Catalog: Spartan?-6 LXT
Other Names: 122-1775XC6SLX45T-2FGG484C-NDXC6SLX45T2FGG484C
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Spartan-6 Family Overview  
DS160 (v2.0) October 25, 2011  
Product Specification  
General Description  
The Spartan?-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The  
thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous  
Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that  
delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input look-  
up table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation  
DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO? technology, power-  
optimized high-speed serial transceiver blocks, PCI Express? compatible Endpoint blocks, advanced system-level power management  
modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a low-  
cost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for  
high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the  
programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable  
designers to focus on innovation as soon as their development cycle begins.  
Summary of Spartan-6 FPGA Features  
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Spartan-6 Family:  
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Integrated Memory Controller blocks  
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Spartan-6 LX FPGA: Logic optimized  
Spartan-6 LXT FPGA: High-speed serial connectivity  
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DDR, DDR2, DDR3, and LPDDR support  
Data rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)  
Multi-port bus structure with independent FIFO to reduce  
design timing issues  
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Designed for low cost  
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Multiple efficient integrated blocks  
Optimized selection of I/O standards  
Staggered pads  
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Abundant logic resources with increased logic capacity  
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Optional shift register or distributed RAM support  
Efficient 6-input LUTs improve performance and  
minimize power  
High-volume plastic wire-bonded packages  
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Low static and dynamic power  
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LUT with dual flip-flops for pipeline centric applications  
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45 nm process optimized for cost and low power  
Hibernate power-down mode for zero power  
Suspend mode maintains state and configuration with  
multi-pin wake-up, control enhancement  
Lower-power 1.0V core voltage (LX FPGAs, -1L only)  
High performance 1.2V core voltage (LX and LXT  
FPGAs, -2, -3, and -3N speed grades)  
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Block RAM with a wide range of granularity  
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Fast block RAM with byte write enable  
18 Kb blocks that can be optionally programmed as two  
independent 9 Kb block RAMs  
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Clock Management Tile (CMT) for enhanced performance  
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Low noise, flexible clocking  
Digital Clock Managers (DCMs) eliminate clock skew  
and duty cycle distortion  
Phase-Locked Loops (PLLs) for low-jitter clocking  
Frequency synthesis with simultaneous multiplication,  
division, and phase shifting  
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Multi-voltage, multi-standard SelectIO? interface banks  
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Up to 1,080 Mb/s data transfer rate per differential I/O  
Selectable output drive, up to 24 mA per pin  
3.3V to 1.2V I/O standards and protocols  
Low-cost HSTL and SSTL memory interfaces  
Hot swap compliance  
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Sixteen low-skew global clock networks  
Adjustable I/O slew rates to improve signal integrity  
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Simplified configuration, supports low-cost standards  
High-speed GTP serial transceivers in the LXT FPGAs  
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2-pin auto-detect configuration  
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Up to 3.2 Gb/s  
Broad third-party SPI (up to x4) and NOR flash support  
Feature rich Xilinx Platform Flash with JTAG  
MultiBoot support for remote upgrade with multiple  
bitstreams, using watchdog protection  
High-speed interfaces including: Serial ATA, Aurora,  
1G Ethernet, PCI Express, OBSAI, CPRI, EPON,  
GPON, DisplayPort, and XAUI  
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Integrated Endpoint block for PCI Express designs (LXT)  
Enhanced security for design protection  
Low-cost PCI? technology support compatible with the  
33 MHz, 32- and 64-bit specification.  
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Unique Device DNA identifier for design authentication  
AES bitstream encryption in the larger devices  
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Faster embedded processing with enhanced, low cost,  
MicroBlaze? soft processor  
Industry-leading IP and reference designs  
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Efficient DSP48A1 slices  
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High-performance arithmetic and signal processing  
Fast 18 x 18 multiplier and 48-bit accumulator  
Pipelining and cascading capability  
Pre-adder to assist filter applications  
? 2009–2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States  
and other countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.  
DS160 (v2.0) October 25, 2011  
Product Specification  
1
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